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30 积分 2023-11-27 加入
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference
14天前
已完结
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple
14天前
已完结
A 10-b 50-MS/s 820-$\mu $W SAR ADC With On-Chip Digital Calibration
17天前
已完结
A semi-synchronous SAR ADC with variable DAC settling time using a DLL
17天前
已完结
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques
17天前
已完结
A 14-nm Low-Cost IF Transceiver IC with Low-Jitter LO and Flexible Calibration Architecture for 5G FR2 Mobile Applications
3个月前
已完结
Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit
9个月前
已完结
A Watt level, 5-7GHz all digital polar TX based on 3.3V switched capacitor digital PA in 16nm Fin-FET for Wi-Fi7 applications
9个月前
已完结
A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer
9个月前
已完结
Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit
9个月前
已完结
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