Lv61
2700 积分 2020-06-16 加入
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment
2个月前
已完结
Gain- and offset-compensated switched-capacitor filters
3个月前
已完结
A 16-bit low-voltage CMOS A/D converter
3个月前
已完结
Offset and clock-feedthrough compensated switched-capacitor integrators
3个月前
已完结
Switched-capacitor circuits with reduced sensitivity to amplifier gain
3个月前
已完结
Spike-free switched-capacitor circuits
3个月前
已完结
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation
4个月前
已完结
A Sub-1 ppm/°C Bandgap Voltage Reference With High-Order Temperature Compensation in 0.18-μm CMOS Process
6个月前
已完结
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration
6个月前
已完结
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