Lv44
470 积分 2025-01-27 加入
Design of High-Speed Communication Circuits
28天前
已完结
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator
2个月前
已完结
An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability
2个月前
已完结
An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-psrms-Integrated-Jitter Degradation With SSC Capability
4个月前
已完结
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment
4个月前
已完结
A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme
4个月前
已完结
28-nm FD-SOI CMOS Submilliwatt Ring Oscillator-Based Dual-Loop Integer-N PLL for 2.4-GHz Internet-of-Things Applications
4个月前
已完结
A (0.75–1.13) mW and (2.4–5.2) ps RMS Jitter Integer-N-Based Dual-Loop PLL for Indoor and Outdoor Positioning in 28-nm FD-SOI CMOS Technology
4个月前
已完结
A 6GHz Sub-Sampling Phase-Locked Loop Using a Lock Detector Controller
4个月前
已完结
Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL
6个月前
已完结
皖公网安备34019202002308
