Lv3
240 积分 2023-10-15 加入
Yield and speed optimization of a latch-type voltage sense amplifier
1天前
待确认
1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture
1天前
待确认
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM
1天前
已完结
An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference
1天前
已完结
Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing
1天前
已完结
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM
22天前
已完结
A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging
22天前
已完结
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
22天前
已完结
A 0.7e<sup>&#x2212;</sup><inf>rms</inf>-temporal-readout-noise CMOS image sensor for low-light-level imaging
3个月前
已完结
Study of $2 \times 4 \mu\mathrm{m}$ Pitch Capsule Shaped TSVs and $2 \mu \mathrm{m}$ Pitch Tsvs in WoWoW Integration
3个月前
已完结
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