Lv7
4194 积分 2020-10-01 加入
A Power-Efficient Three-Stage Dynamic Comparator for Wide Input Common-ModeRange
1个月前
已完结
Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS
1个月前
已完结
An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators
1个月前
已完结
A 0.69-Noise-Efficiency-Factor 55× -Preamp-Gain Dynamic Comparator With a Stacking FIA
1个月前
已完结
A 14b 500MS/s Pipelined-SAR ADC with Loop-Unrolled Correlated Level Shifting and Rapid Sequential Sampling
1个月前
已完结
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier
1个月前
已完结
A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration
1个月前
已完结
Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density
4个月前
已完结
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer
4个月前
已完结
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
4个月前
已完结
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