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160 积分 2020-05-20 加入
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires
1年前
已完结
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber
1年前
已完结
A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE
1年前
已完结
A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY
1年前
已完结
A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY
1年前
已关闭
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
2年前
已完结
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process
2年前
已完结
A 1.2 Gbps failsafe low jitter LVDS transmitter-receiver applied in CMOS image sensor
2年前
已完结
A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system
2年前
已完结
A 622 MHz stand-alone LVDS driver pad in 0.18-μm CMOS
2年前
已完结
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