Lv7
4760 积分 2024-05-20 加入
An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing
3小时前
待确认
An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory
3小时前
已完结
How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!
3小时前
已完结
RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory
3小时前
已完结
A Fully Row/Column-Parallel MRAM In-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout
3小时前
待确认
A 28-nm 18.7 TOPS/mm$^2$ 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
5个月前
已完结
eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations
5个月前
已完结
Operation Scheme Optimizations to Achieve Ultrahigh Endurance (10$^{\text{10}}$) in Flash Memory
6个月前
已完结
Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part II: Adaptive Layer-Wise Refresh Technique
6个月前
已完结
Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure
6个月前
已完结
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