Lv7
3730 积分 2021-07-05 加入
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction
3小时前
待确认
SPICE based SI-PI co-simulation Framework to optimize Die-Package-PCB to meet LPDDR5(x) Performance in Automotive and Edge MPU-MCU
3小时前
待确认
Impact of DBI Feature on Peak Distortion Analysis of LPDDR5 at 6400Mbps
3小时前
待确认
Overcome the IBIS Model Overclocking Issue for SDRAM Interface
3小时前
待确认
Crosstalk Analysis for Symmetric and Asymmetric High-Speed Signal Lines of GDDR6 Package
3小时前
待确认
Design space exploration (DSE) for over-136GB/s IO bandwidth with LPDDR5X SDRAM packages on SOC package in 200mm3
3小时前
待确认
Tabbed Routing Modeling and Design Optimization for High-speed Signaling Channel
1个月前
已完结
Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation
4个月前
已完结
Thermal-Aware Scheduling for Deep Learning on Mobile Devices With NPU
4个月前
已完结
Online Scheduling of CPU-NPU Co-inference for Edge AI Tasks
4个月前
已完结
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