Lv7
3600 积分 2021-07-05 加入
IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
7小时前
待确认
A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage
1个月前
已完结
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM
1个月前
已完结
SparseDroop: Hardware–Software Co-Design for Mitigating Voltage Droop in DNN Accelerators
1个月前
已完结
37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE
2个月前
已完结
13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction
2个月前
已完结
A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode
2个月前
已完结
A digital dynamic power monitor based adaptive clocking system for voltage droop mitigation in 5nm mobile application processor
2个月前
已完结
Optimizing Power and Power Delivery For Data Center GPUs
2个月前
已完结
Determining PCIe5 Jitter Margin using SIPI Co-Sim
5个月前
已完结
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