Timing‐Dependent Spiking Neural Network: Board‐Level Hardware Implementation with Photoelectroactive Van der Waals Synapses

作者
Seong-Jun Kim,Jeong‐Ick Cho,Sungsoo Lee,Yoonchul Shin,Je Jun Lee,Tae-Hyuk Jang,Hyeon-Jung Kim,Jun-Hwa Oh,SangHyun Lee,Kwanghee Ko,Juncheol Kang,Junseo Lee,Matthew T. Flavin,Dong Ho Kang,Byung Chul Jang,Ji Hoon Ahn,Yoonmyung Lee,Sang Min Won,Jin-Hong Park,Seyong Oh
出处
期刊:Advanced Materials [Wiley]
卷期号:: e17613-e17613
标识
DOI:10.1002/adma.202517613
摘要

Abstract The rapid growth of unstructured data in applications such as autonomous systems and edge AI underscores the urgent need for energy‐efficient, real‐time computing exemplified by biological brains, where synaptic weights are adjusted according to the timing of neural spikes, known as spike‐timing‐dependent plasticity (STDP). This work presents the first experimental realization of a multi‐channel timing‐dependent spiking neural network (TD‐SNN) at the board‐level by integrating photoelectroactive synaptic devices with an analog leaky integrate‐and‐fire (LIF) neuron circuit. The synaptic devices exploit the precise timing dependency between electrical presynaptic and optical postsynaptic spikes to emulate STDP, enabling reversible and bidirectional modulation of synaptic weights through photoelectroactive doping. By engineering the shape of presynaptic pulses, the devices demonstrate diverse biological STDP learning rules, including Hebbian, anti‐Hebbian, all‐LTP, and all‐LTD. Integrated single‐ and multi‐channel networks exhibit self‐learning, system‐level adaptive, and competitive behaviors. Experimentally extracted STDP parameters are implemented in SNN simulations, where network performance is determined by the long‐term potentiation/depression area ratio (LTP/D area ratio, PDR ) of the STDP curve. When PDR ≥ 1.25, robust pattern classification is achieved, reaching up to 90.9% accuracy on MNIST tasks. These results mark a milestone in timing‐dependent neuromorphic hardware, demonstrating device‐level feasibility toward adaptive and real‐time learning hardware.
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