Modeling and Understanding of External Latchup in CMOS Technologies—Part II: Minority Carrier Collection Efficiency

The n-wells of the parasitic p-n-p-n devices found in a CMOS layout will collect excess minority carriers from the chip substrate, potentially triggering latchup. This paper presents a model for the minority carrier collection efficiency of a given substrate current injector and collector pair; the model captures the effects of spacing, supply voltage, temperature, and current level. The model further describes the quantitative reduction in collection efficiency obtained by using guard rings. A good fit of the model to measurement results is observed in four different CMOS technologies.