国际商用机器公司
计算机科学
一套
可靠性(半导体)
脆弱性(计算)
估计
可靠性工程
嵌入式系统
计算机体系结构
功率(物理)
工程类
系统工程
材料科学
物理
计算机安全
考古
量子力学
历史
纳米技术
作者
Karthik Swaminathan,Ramon Bertran,Hans Jacobson,Pradip Bose,Matthias Pflanz,Doug Balazich
标识
DOI:10.1109/dsn-s52858.2021.00033
摘要
Early stage modeling of processor reliability is a key feature in the design and manufacturing cycle of IBM server-class processors. In this paper, we present SERMiner, a highly adaptable methodology for early-stage processor reliability estimation. We demonstrate how this methodology can be used to evaluate potential processor vulnerability to soft errors. We carry out extensive evaluations to determine the vulnerability across a comprehensive suite of synthetic and real-world benchmarks and also show how this estimation evolves across different processor generations and stages of design.
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