Analysis of Single-Event Transient in Tunneling-Based Ternary CMOS With Gate-All-Around Structure

In this study, single-event transient (SET) characteristics in tunneling-based ternary complementary MOS device (T-CMOS) with gate-all-around structure (i.e., nanosheet FET) were analyzed for the first time. For low power computing systems, the transition from binary to ternary logic systems has been proposed as a solution to surmount the power density limitations inherent in conventional CMOS technology and to enhance their integration capabilities. As a part of this exploration, tunneling-based T-CMOS technologies have been extensively investigated. However, the susceptibility of those T-CMOS devices to radiation-induced effects has remained largely unexplored. Therefore, we evaluated soft error effects by observing SETs induced by heavy-ion effects in the T-CMOS inverters using 3D TCAD simulation. To clearly understand electrical characteristics related to SET effects for ternary logic system, the binary CMOS (B-CMOS) inverter was used as a reference. Then, it was revealed that the T-CMOS inverter is more vulnerable to heavy-ion effects, especially for $V_{\mathrm {OUT}} = {MID}_{\mathrm {TERNARY}}$ state, compared to the B-CMOS inverter. This is because of smaller state margin as well as lower current drivability by implementing three states. Also, SET characteristics were evaluated with variations in ground plane doping concentrations ( $N_{\mathrm {GP}}$ s), which is a key process parameter related to ${MID}_{\mathrm {TERNARY}}$ state by tunneling components. Then, it was confirmed that higher $N_{\mathrm {GP}}$ makes recovery process faster, resulting in mitigating soft errors. From these results, it would be very helpful to get valuable insights for the design of the T-CMOS inverter in terms of soft errors.