Thousands of conductance levels in memristors integrated on CMOS

记忆电阻器 计算机科学 CMOS芯片 神经形态工程学 电阻随机存取存储器 人工神经网络 电导 集成电路 GSM演进的增强数据速率 记忆晶体管 纳米技术 电子工程 电气工程 材料科学 人工智能 电压 工程类 物理 操作系统 凝聚态物理
作者
Mingyi Rao,Hao Tang,Jiangbin Wu,Wenhao Song,Max Zhang,Wenbo Yin,Ye Zhuo,Fatemeh Kiani,Benjamin K. Chen,Xiangqi Jiang,Hefei Liu,Hung‐Yu Chen,Rivu Midya,Fan Ye,Hao Jiang,Zhongrui Wang,M Wu,Miao Hu,Han Wang,Qiangfei Xia
出处
期刊:Nature [Nature Portfolio]
卷期号:615 (7954): 823-829 被引量:264
标识
DOI:10.1038/s41586-023-05759-5
摘要

Neural networks based on memristive devices1–3 have the ability to improve throughput and energy efficiency for machine learning4,5 and artificial intelligence6, especially in edge applications7–21. Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks22–28. This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even ‘mortal computing’25,29,30. Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications. Chips with 256 × 256 memristor arrays that were monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry achieved 2,048 conductance levels in individual memristors.
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