Gate/Drain Stress Interplay in Low-Voltage Schottky-Type p-GaN Gate HEMTs during Switching Operation

This work reveals the interplay between the gate and drain stresses on the dynamic threshold voltage (VTH) behavior in a commercial low-voltage Schottky-type p-GaN gate high electron mobility transistor (HEMT) featuring a fully depleted p-GaN layer. Under VDSstress alone, the dynamic VTHshift exhibits an unsaturated positive shift with increasing stress time, attributed to the gradual ionization of deep-level traps within the gate stack. In contrast, VGSstress induces a transition from positive to negative VTHshift as VGSincreases, indicating competing mechanisms between electron trapping and hole injection from the gate. Under mixed VGS/VDSstress, the resulting dynamic VTHshift manifests as a nonlinear superposition of the individual VGSand VDSinduced shifts. Notably, at a VGSof 5 V, a positive VTHshift of 0.7 V is observed after 1000-s stress, yet the VTHshift is reduced to 0.35 V as VGSincreases to 7 V. Consequently, operating the device in the RONsaturation regime at higher VGS(i.e., 6 V) can effectively mitigate RONdegradation induced by positive VTHshift.