Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators

Comparator power consumption is a major bottleneck to the power efficiency of a high resolution successive approximation register (SAR) analog-to-digital converter (ADC) used in low-power applications. This paper analyzes theoretically the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels. A simple and accurate mathematical model of the SAR ADC that is amenable to analysis is first presented. The mathematical formulation suggests that the comparison power allocated to each bit step need not be the same. The optimization problem, therefore, is solved so that the comparator power budget is optimally distributed among all bit steps. Simulation results show that up to 50% and 60% power savings can be achieved when 10 and 12 comparators are employed for 10 b and 12 b SAR ADCs, respectively. To reduce the implementation complexity, comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators is sufficient to achieve near ideal performance in 10 b and 12 b SAR ADCs.