Failure analyses of 3D Sip (system-in-package) and WLP (wafer-level package) by finite element methods

In this study, three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the filled copper; (2) the failures of the microbumps between the fine-pitch IC chip and the TSV interposer (chip) due to the global thermal expansion mismatch between the silicon IC Chip and the copper filled TSV interposer (chip); and (3) the failures of leadfree solder joints of a wafer-level chip scale package (WLCSP) due to the thermal expansion mismatch between the silicon WLCSP and the FR-4 epoxy printed circuit board (PCB). The results show that finite element method is not only able to identify the failure locations and determine the stress and strain to cause failures but also perform design for reliability.