Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating

Three-dimensional (3D) microsystem integration offers solutions for improved device functionality, increased bandwidth per volume, simplified design and assembly, and system miniaturization. Through-silicon vias (TSVs) are a key technology for incorporating devices into 3D integration schemes. Microelectromechanical systems (MEMS) applications often utilize full thickness silicon substrates, creating a need for mesoscale TSVs (> 0.5 mm thick) at high aspect ratios (> 5:1) to facilitate demands of increased interconnect density. Copper (Cu) is a preferred material for TSV filling because of its high electrical and thermal conductivity and can be deposited through electrochemical deposition (ECD) to fill high aspect ratio features. Although Cu ECD has been historically performed using three additive systems, recent work has demonstrated that Cu deposition can be achieved in a simplified CuSO 4 -H 2 SO 4 electrolyte system with only a single suppressor additive and halide salt. [i] , [ii] The cyclic voltammetry (CV) scan for this electrolyte exhibits s-shaped negative differential resistance (S-NDR), observed as hysteresis in the CV voltage-current relationship between forward and reverse scans. Hysteretic voltammetry indicates bifurcating behavior in the electrolyte system, where bottom-up filling is possible in the vias, while the field surface remains passivated. In systems with limited suppression, performing ECD with a sustained potential leads to localized Cu deposition at specific depths within the vias. An increasingly negative potential waveform can be implemented to progressively move deposition vertically through the vias. Achieving a bottom-up, void-free fill with these additive-based electrolytes is typically performed through potentiostatic plating with a reference electrode. Scaling these processes from die level plating experiments, in a small electrochemical cell, to a production-scale full-wafer plating tool requires development of a current-controlled plating regime, because production tools are not equipped with reference electrodes. Furthermore, the developed plating process cannot be highly sensitive to sample rotation rate, because vias at various radial positions across a wafer move at different speeds. In this work, we describe the development of a current-controlled deposition process for bottom-up, void-free filling and further scale this plating process from 1 cm 2 sample sizes to a full 150 mm diameter wafer. Voltage-controlled ECD parameters were first established with die level plating experiments. This voltage-controlled process was used to derive a current-controlled ECD procedure, which was followed by sample size scaling experiments and rotation rate studies. The TSV geometries for these experiments had a 10:1 aspect ratio, with via diameters of 62.5 µm, etched into a 625 µm thick silicon substrate. These vias were successfully filled with a potential stepping regime in which the voltage started at -500 mV (MSE) and was gradually incremented to -560 mV (MSE) using -10 mV steps. Time duration at each potential ranged from 2 to 5 hours to achieve a void-free fill. During these voltage-controlled Cu deposition experiments, the resulting current was measured. Subsequent plating experiments were executed by applying current, as opposed to voltage, to mimic the measured current values, and this current-controlled ECD process also achieved void-free filling. Figure 1 shows the development process from voltage-controlled to current-controlled ECD and corresponding mechanical cross sections. As shown in the sample cross sections, these electroplating processes result in fully suppressed deposition on the field area, even though the field is part of the total conducting surface. It was hypothesized that current density scales with via area, as opposed to total conductive surface area; therefore, scaling experiments were performed to understand the relationship between applied current density, total conductive surface area, and active via area. Additionally, with a wafer rotating about its center, solution replenishment within each via is dependent on its radial position. To understand the dependence on solution replenishment and applied bias in a given electrolyte, a series of investigations were performed on samples rotated at different rates. This work presents the results of these studies for establishing a wafer level plating process for 10:1 aspect ratio TSVs. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2020-5515 C [i] D. Josell and T. P. Moffat, Journal of The Electrochemical Society, 165 (2) D23-D30 (2018). [ii] L. A. Menk, D. Josell, T. P. Moffat, E. Baca, M. G. Blain, A. Smith, J. Dominguez, J. McClain, P. D. Yeh, and A. E. Hollowell, Journal of The Electrochemical Society, 166 (1) D3066-D3071 (2019). Figure 1