Porous Silicon Fabrication and Surface Cracking Behavior Research Based on Anodic Electrochemical Etching▴

Abstract Porous silicon (PSi) was fabricated based on anodic electrochemical etching, and the relationship between preparation conditions, nanostructure and PSi surface crack behavior were systematically studied. The effects of silicon wafer resistivity (doping concentration), etching time, and etching current density on nanostructure of PSi were investigated. Results indicated that lower resistivity was beneficial to etching process and led to higher porosity with uniform nano‐channels, and surface crack was more intense during drying process. Thickness and porosity of the porous layer are both initially increased and then decreased with increasing etching time. Direction of capillary stress depended on pore geometry, which further affected crack shape (shrinkage or crimp) of surface layer of PSi. Cracking extent was controlled by porosity, that the surface cracking layer began to peel off when the porosity exceeded 70%. Finally, a geometry and porosity‐controlled model was proposed to describe the cracking behaviors of PSi surface layer.