Formation and Evolution Mechanism of Dislocation Piles Induced by Triangle Defects in Thick 4H–SiC Epilayers

位错 薄脆饼 材料科学 垂直的 外延 碳化硅 滑翔机 基面 凝聚态物理 基质(水族馆) 结晶学 平面(几何) 半导体 复合材料 部分位错 位错蠕变 热的 碳化物 晶体缺陷 蚀刻(微加工) 皮尔斯应力 光学 制作
作者
Xiyao Huang,Mingsheng Xu,Xinyue Hou,Shan Yang,Yifei Chen,Yapeng Guo,孙立贤,Shuqiang Li,Ling Guo,Jisheng Han,Xiaobin Xu
出处
期刊:Crystal Growth & Design [American Chemical Society]
卷期号:26 (3): 1301-1308 被引量:1
标识
DOI:10.1021/acs.cgd.5c01478
摘要

4H Silicon carbide (4H–SiC) is the most promising semiconductor for power devices. The performance of the devices is determined by the quality of the 4H–SiC epilayers. Triangle defects are the most prevalent defects in the epilayers. As the epilayer thickness increases, more defects are generated in association with them, further leading to a decrease in device yield. In this work, the formation and evolution mechanism of dislocation piles derived from triangle defects in thick epilayers is investigated. The composition of the 3C silicon carbide (3C–SiC) in the triangle defects was confirmed by Raman spectroscopy. The dislocation piles originate from basal plane dislocation (BPD) segments generated by the mismatch between 3C–SiC and 4H–SiC. Based on X-ray topography (XRT) measurements, it is determined that the dislocation piles consist of interfacial dislocations (IDs), BPDs, and threading dislocations (TDs). The evolution mechanism of dislocation piles was analyzed by three-dimensional (3D) XRT section images, and a model was established. The BPD segments generated by mismatch glide under thermal stress, leaving IDs at the interface between the substrate and the epilayer. The glided BPDs continue to propagate along the basal plane with epitaxial growth and are converted into TDs under the step-flow. TDs propagate perpendicular to the basal plane and reach the surface of the epilayer, leaving growth pits on the surface. This study conducts an in-depth investigation into the formation, evolution, and effects of dislocation piles induced by triangle defects in a thick 4H–SiC epilayer, providing guidance for further improving wafer yield.
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