德拉姆
材料科学
光电子学
外延
蚀刻(微加工)
纳米技术
图层(电子)
作者
Zhenzhen Kong,Hongxiao Lin,Hailin Wang,Yao Song,Junjie Li,Xiaomeng Liu,Anyan Du,Yuyang Miao,Yiwen Zhang,Yuhui Ren,Chen Li,Jiahan Yu,Jinbiao Liu,Jingxiong Liu,Qingzhu Zhang,Jianfeng Gao,Huihui Li,Xiangsheng Wang,Junfeng Li,Henry H. Radamson,Chao Zhao,Tianchun Ye,Guilei Wang
出处
期刊:Journal of Semiconductors
[IOP Publishing]
日期:2023-12-01
卷期号:44 (12): 124101-124101
标识
DOI:10.1088/1674-4926/44/12/124101
摘要
Abstract Fifteen periods of Si/Si 0.7 Ge 0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si 0.7 Ge 0.3 features the best crystal quality and no defects are observed. Stacked Si 0.7 Ge 0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.
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