A 14b 180MS/s Pipeline-SAR ADC with Adaptive-Region-Selection Technique and Gain Error Calibration

This brief presents a 70.6-dB SNDR pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes an Adaptive-Region-Selection (ARS) technique to linearize the residue amplification. The proposed technique avoids the complex high-order nonlinearity detection and correction in the digital domain, while the final ADC output only necessitates a simple and pre-defined offset code compensation. The inherent hardware of the proposed ARS technique also facilitates a simple gain calibration solution that corrects both inter-stage gain error and the first-order nonlinearity. The prototype pipeline-SAR ADC was fabricated in a 28-nm CMOS process. The presented ARS technique improves the peak SNDR by >7 dB, and reduces the worst case differential non-linearity (DNL)/integrated non-linearity (INL) by 3.6 times.