Thermo-mechanical reliability of 3-D ICs containing through silicon vias

In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses in silicon decrease as a function of distance from an isolated TSV and increase with the TSV diameter. Additional simulation suggested that hybrid TSV structures can significantly reduce the thermal stresses. An analytical stress solution was introduced to deduce the stress distribution around an isolated TSV, which was further developed to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. We calculated the crack driving force in TSV lines under a thermal load. The effects of TSV diameter, pitch size, and the line configuration on crack driving force were investigated.