An Improved FIPS Algorithm for Pipeline Structure and Its Implementation

VLSI implementation of multiplier and accumulator based on FIPS was investigated.Differences in speed and area of implementations based on different operand width were analyzed.To solve the data latency problem caused by the pipeline data path, an improved FIPS algorithm was presented.And a modular multiplier with an operand width of 128 bits was designed based on the improved FIPS in 0.18 μm CMOS technology.Compared with designs based on the original FIPS, the optimized design achieved a 42% of speed improvement with only 5% of area increase.With the modular multiplier, a decryption rate of 1.1 Mbps could be achieved for 1 024-bit RSA.