Decoupled Layout Approach for Paralleling GaN Devices in Half Bridge Inverters

To increase power capability or to achieve higher efficiencies in power converters multiple GaN devices need to be paralleled. Diverse parasitics of the power stage and gate driver circuits, which are very sensitive to the high di/dt and dv/dt during the switching process are main challenges for parallel operation. This makes PCB layout and gate drive design very challenging. Unbalanced loss distribution among paralleled switches could cause overtemperature issues which can result in device failure or system derating. A novel decoupled PCB structure for paralleling GaN devices is presented in this paper. The proposed structure enables optimum dynamic current sharing and reduces voltage overshoots and current oscillations. A 2kW half bridge power stage consisting of two high side and two low side GaN devices in parallel has been built and validated. Both enhancement mode and Cascode GaN devices in parallel mode of operation have been based on the decoupled PCB layout approach. Peak efficiency of ninety eight percent has been demonstrated.