A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM

Computing-in-memory (CIM) is a promising paradigm for energy- and area-efficient implementation of the heavy general matrix multiplication (GEMM) operations, especially in the evolving deep learning algorithms. Though existing CIM macros have demonstrated remarkable energy/area efficiency, the corresponding metrics of the system-level CIM chips degrade due to the peripheral components, including external SRAM and accumulation circuits. First, the separated design of CIM macros and peripheral components leads to suboptimal solutions, suffering high input/output SRAM access power, loose layout with long data paths, bulk clock trees, and so on. Second, the input/output SRAM takes a majority area proportion, which is inevitable in existing system-level CIM chips. Besides, continuous power/area optimization on the CIM macro itself also contributes to the system-level energy/area efficiency. Third, the accumulation module after the CIM macro leads to redundant power consumption due to the unnecessary high-bit-position computation. This work presents a system-in-one-macro CIM chip, integrating all system-level components (except the control logic) into one single macro, indicating a significant difference in the design flow with three detailed innovations: 1) to replace the power/area consuming external SRAMs, a high-density leakage-eliminated 2T1C embedded DRAM (eDRAM) is designed for input activation and output result storage; 2) a capacitor (cap)-over-logic one-transistor-one-capacitor (1T1C) eDRAM array with shared-preprocessing MUX-based CIM circuits is proposed to further improve the macro-level CIM energy/area efficiency and density; and 3) utilizing the low-activity property of the high-bit-position accumulation, a low-MAC-aware near-memory-computing (NMC) circuit is designed to reduce the redundant accumulation power. The 28-nm fabricated system-in-one-macro CIM chip demonstrates 51.6 TOPS/W energy efficiency, 1.53 TOPS/mm² area efficiency, and 2.22-Mb/mm² storage density.