EPE budget analysis and margin co-optimization on the multiple critical on-device features in a single image for yield enhancement

The advanced logic node is continuously shrinking toward 1nm and EUV lithography is one of the main technical drivers to reach better patterning resolution combined with reduced process steps. Along with this design rule shrink, the patterning control with the metric of Edge Placement Error (EPE), of which main contributors are CD and overlay error, becomes more and more critical. EPE-aware process margin studies1 are of growing interest and focus on advanced nodes. However, the studies are mostly focused on single type of device feature or hot spot (HS) and the EPE budget breakdown is analyzed through the data set from different process steps, metrology tools (SEM, OM), and measurement targets (device structure, scribe line target) which inherently contains the problem of data integrity and proximity2. Due to the complicated and localized process loading of the various pattern on logic device the EPE analysis is required on diverse critical device features (HS's) which shows different fingerprint of EPE due to the process loadings and multi-patterning effects among unit process characteristics. To accomplish this multiple HS EPE-aware analysis, the measurement must be taken at various real device pattern. This requirement leads to data collection with an e-beam tool, using high electron landing energies while utilizing the ElluminatorTM technology for improvement backscattered electrons (BSE) imaging efficiency. This is the unique and right approach to directly capture CD and overlay simultaneously in die, on device, multiple HS's in local and global level. In this paper, we will demonstrate the EPE budget analysis on various on device HS which results in the different process fingerprint due to the local process loading effect. The all-in-one and on device pattern measurement is the essential prerequisite capability on this study. The data is captured from the high-quality e-beam image which delivers a CD-SEM comparable precision, low TMU overlay metrology on real device. We demonstrate that with the multi HS EPE-aware analysis from the all-in-one on device data, the balanced EPE margin is achieved through the co-optimized correctable with the weighted factors among HS's to increase yield at end of line. Keywords: CD, Overlay, e-beam, EPE, accuracy, on device, HS, yield