Modeling the development of low current arcs and arc resistance simulation

Low current arcs in the range 0.5 ∼5 mA occur in power networks in situations such as on overhead line insulators and cable terminations. These arcs are important because of their potential contribution to surface ageing, asset failure and potential flashover. In this paper, the development of low current arcs is classified in three stages: a formative leakage current phase (∼μΑ), a stage where discharges occur but are unstable with each half power cycle (<1 mA) and a period of stable discharges (>1 mA). Arc resistance is a key element in controlling arc behavior in each stage, and is modeled as the combination of a stable arc resistance, an oscillating resistance and a surface resistance. The resulting arc model has been developed in PSCAD/EMTDC, to simulate an arc/discharge in each development stage. Simulations compare well with experimental data. The simulation reveals that peak arc current plays a key role in the transition from an unstable to stable arc. Analysis shows a significant increase in discharge energy as a result of its stabilization. These models explain the conditions required for accelerated ageing of polymeric insulators and can be used to design and interpret testing regimes, and for polymeric insulator asset management.