Development of an inkjet-enabled adaptive planarization process

化学机械平面化 抵抗 薄脆饼 材料科学 光刻 纳米压印光刻 平版印刷术 基质(水族馆) 纳米技术 过程(计算) 计算机科学 光电子学 制作 图层(电子) 病理 地质学 替代医学 操作系统 海洋学 医学
作者
Niyaz Khusnatdinov,Shrawan Singhal,S. V. Sreenivasan,Douglas J. Resnick,Michelle Grigas
标识
DOI:10.1117/12.2280311
摘要

Nanoimprint lithography manufacturing utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Throughputs of 80 wph have been demonstrated, and mix and match overlay of 3.7nm 3 sigma has been achieved. The technology has already been successfully applied as a demonstration to the fabrication of advanced NAND Flash memory devices. A similar approach can also be applied however to remove topography on an existing wafer, thereby creating a planar surface on which to pattern. In this paper, a novel adaptive planarization process is presented that addresses the problems associated with planarization of varying pattern densities, even in the presence of pre-existing substrate topography. The process is called Inkjet-enabled Adaptive Planarization (IAP). The IAP process uses an inverse optimization scheme, built around a validated fluid mechanics-based forward model that takes the pre-existing substrate topography and pattern layout as inputs. It then generates an inkjet drop pattern with a material distribution that is correlated with the desired planarization film profile. This allows a contiguous film to be formed with the desired thickness variation to cater to the topography and any parasitic signatures caused by the pattern layout. In this work, it was demonstrated that planarization efficiencies of up to 99.5% could be achieved, thereby reducing an initial ~100nm wafer topography down to as little as 0.6nm.
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