可靠性(半导体)
扇出
中间层
集成电路封装
薄脆饼
芯片级封装
晶圆级封装
球栅阵列
电子工程
炸薯条
计算机科学
成套系统
嵌入式系统
材料科学
工程类
焊接
图层(电子)
电气工程
电信
纳米技术
物理
功率(物理)
量子力学
复合材料
蚀刻(微加工)
作者
Min Jung Kim,Seok Hyun Lee,Kyoung Lim Suk,Jae Gwon Jang,Gwang‐Jae Jeon,Ju-il Choi,Hyo Jin Yun,Jongpa Hong,Ju-Yeon Choi,Won Jae Lee,Sukhyun Jung,Won Kyoung Choi,Dae-Woo Kim
出处
期刊:Electronic Components and Technology Conference
日期:2021-06-01
卷期号:: 321-326
被引量:19
标识
DOI:10.1109/ectc32696.2021.00061
摘要
Advances in the high performance computing (HPC) lead to a new frontier of the fan out wafer level packaging (FOWLP) development. To provide a solution of cost-attractive package for heterogeneous chip integration, FOWLP has recently emerged as an indispensable platform. Herein, we propose novel 2.5D re-distribution layer (RDL) interposer packaging technology including the fabrication of fine-pitch RDL interposer (>560 mm 2 ) assembled with one high-bandwidth memory (HBM) and two ASICs, in order to achieve the TSV-less and cost-effective package. The intrinsic features of the fine-pitch RDL interposer enhances the integrity of the signals and the reliability of the bump joints, and thus integrates multiple chips and accommodates higher I/O counts. With the fine-pitch 2.5D RDL interposer technology, the system-in-package is fabricated in order to substantiate the functions of the HBM, and tested to analyze the characteristics of its performance. The fine-pitch 2.5D RDL interposer package demonstrates up to 3.2Gbps/pin operation with the HBM, and also shows excellent reliability without any failure during the reliability tests (TC1000hr, b-HAST 264hr, u-HAST 264hr and HTS1000hr). The proposed 2.5D RDL interposer technology can be a promising solution for the cost-effective and large size 2.5D packaging in the HPC applications.
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