p-Type High-Performance WSi2N4 MOSFETs with the Ultrashort Scale of Sub-5 nm

In this article, we explore the ballistic transport limits of p- and n-type monolayer (ML) WSi2N4 metal-oxide-semiconductor field-effect transistors (MOSFETs) at the sub-5 nm scale. The results show that varying the doping concentration, gate length, and underlap region (LUL) structure can effectively tune the on-state current (Ion) and subthreshold swing (SS) of the WSi2N4 MOSFETs. Notably, Ion, delay time (τ), and power dissipation (PDP) of the optimized p-type WSi2N4 MOSFETs still fulfill the high-performance standard of the International Technology Roadmap for Semiconductors for 2028 until the gate length is minimized to 3 nm. Ion of p-type WSi2N4 MOSFETs with Lg = 5 nm and LUL = 2 nm can be up to 1546 μA/μm. Meanwhile, the SS reaches exactly the thermal limit of 60 mV/dec. We also find that the use of high-k dielectric layers can significantly improve Ion and SS of p- and n-type WSi2N4 MOSFETs. Particularly, under the high-k dielectric layer, Ion of p-type WSi2N4 transistor with gate length Lg = 3 nm without an underlap region is as high as 1550 μA/μm, which is considerably higher than that of other 2D material MOSFETs at the same scale. This work suggests that ML WSi2N4 is highly prospective in the development of p-type high-performance transistors.