A Self-Calibrated Fractional-N PLL for WiFi 6 / 802.11ax in 28nm FDSOI CMOS

This paper presents a fractional-N PLL frequency synthesizer with self-calibration digital loop engines for fast frequency acquisition and noise-driven optimization of loop filter bandwidth, VCO frequency and amplitude control. The PLL is implemented in a 28nm FDSOI CMOS technology and its noise performance is optimized by employing a dual-edge PFD architecture, charge pump linearization, and bias sampling and a spur-less, single-stage multiple feedback sigma delta modulator to achieve a typical rms jitter of 175 fs, while drawing 21 mA from a 1.8-V supply.