CMOS芯片
电子工程
计算机科学
锁相环
电气工程
晶体管
收发机
光电子学
压控振荡器
作者
Gerasimos Vlachogiannakis,Charis Basetas,Georgia Tsirimokou,Chrysoula Vassou,Konstantinos Vastarouchas,Aidonia Georgiadou,Ioulia Sotiriou,Timothea Korfiati,Savvas Sgourenas
出处
期刊:European Solid-State Circuits Conference
日期:2019-09-01
卷期号:: 105-108
被引量:4
标识
DOI:10.1109/esscirc.2019.8902919
摘要
This paper presents a fractional-N PLL frequency synthesizer with self-calibration digital loop engines for fast frequency acquisition and noise-driven optimization of loop filter bandwidth, VCO frequency and amplitude control. The PLL is implemented in a 28nm FDSOI CMOS technology and its noise performance is optimized by employing a dual-edge PFD architecture, charge pump linearization, and bias sampling and a spur-less, single-stage multiple feedback sigma delta modulator to achieve a typical rms jitter of 175 fs, while drawing 21 mA from a 1.8-V supply.
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