Radiation-Immune Spintronic Binary Synapse and Neuron for Process-in-Memory Architecture

This paper proposes an SEU-hardened task-scheduling logic in memory XNOR/XOR neuron and synapse circuits. Using C-element and magnetic tunnel junction enhances immunity against single event upset injection to the design. Also, using logic in memory architecture eliminates the need to access external memory and decreases power and delay. Furthermore, using the carbon nanotube field-effect transistor leads to lower leakage and static current caused by higher gate control in these transistors. Compared to the state-of-the-art counterparts, the proposed design offers at least 31%, 17%, and 3% improvement regarding power, power delay product, and power delay area product