Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization

This paper presents SRAM design methodology that aims to minimize power consumption and/or maximize performance while meeting predefined constraints through Bayesian optimization (BO). The BO process utilizes sigmoid utility functions to consider the constraints. It also uses a power and performance prediction model based on linear regression, as well as a Gaussian process model accumulation to enable efficient optimization of SRAMs with arbitrary capacity. Moreover, the implementation of automatic layout adjustment enables fully automated optimization without requiring manual layout modifications, allowing for more accurate and efficient optimization process that based on post-layout simulations. Simulation results of TSMC 28nm process show that the proposed methodology reduces 6.9%-17.9% of dynamic power and 0.3%–20.3% of access time compared to the design generated by the commercial compiler. Simulation result spend 10–40 hours and there is no compromising other circuit performance metrics.