Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2 Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

In this paper, a La 2 O 3 /HfO 2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (V FB ) negatively shifts 60 mV with sub-1nm La 2 O 3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La 2 O 3 /HfO 2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology.