Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm

Nanowire field-effect transistors (NWFETs) are known to become the emerging transistor type for better performance and low power for future technology nodes beyond 7 nm. Their unique structures allow the transistors to be designed horizontally or vertically, leading to a smaller form factor. However, it is not well studied on how much improvements NWFETs can achieve, especially when vertical FETs (V-NWFETs) are invoked in designs. In this paper, we investigate the advantages that NWFETs provide to standard cell designs. We propose an interconnect structure and a design methodology that optimize design metrics such as area, wirelength, and capacitance of V-NWFET standard cells. Then, we perform comparisons on these design metrics to standard cells between FinFET, horizontal NWFET (H-NWFET), and V-NWFET. This study shows that H-NWFETs achieve significant capacitance reduction compared to the conventional FinFETs (–30.1%). In addition, V-NWFETs achieve even more capacitance reduction (−50.0%), and significant reduction in area (−22.5%) and wirelength (−14.4%) compared to FinFETs. This is possible because (1) fin-to-metal coupling consists of a significant portion in total capacitance and NWFETs contribute to the large reduction of this capacitance and (2) standard cells using V-NWFETs reduce significant area and wirelength compared to conventional FinFET standard cells. However, careful design and proper interconnect structure are required to fully exploit the design advantages.