Hybrid Gate Dielectric of MoS2 Transistors for Enhanced Photo‐Electronic Stability

Abstract MoS 2 thin‐film transistors (TFTs) have been widely studied for use as driving TFTs of active‐matrix displays considering their outstanding electrical advantages such as high mobility and high on/off current ratio. However, due to the atomically thin nature of MoS 2 , the device performance of MoS 2 TFTs suffers from trap sites at the interface. In this study, a hybrid gate dielectric based on an interface engineering strategy using poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3) via initiated chemical vapor deposition is investigated to enhance the negative bias illumination stress (NBIS) stability of MoS 2 TFTs. Compared to a single oxide dielectric layer (Al 2 O 3 ), a hybrid dielectric layer (pV3D3/Al 2 O 3 ) exhibits decreased threshold voltage shift under NBIS by reducing functional groups, such as hydroxyl (OH − ) group, which act as charge trapping sites at the interface between the MoS 2 channel and the gate dielectric. It is confirmed by quantitative analysis using the stretched‐exponential model. Tau (τ), one of the modeling parameters in the stretched‐exponential model, decreases from 210 to 120 s, indicating the improvement in stability. Furthermore, in a low‐frequency noise (1/ f ) measurement, hybrid‐dielectric‐based TFTs show an order of magnitude lower noise power spectral density ( S ID / I D 2 ) than single‐oxide‐dielectric‐based TFTs.