Development of a high-performance readout circuit for photoelectric detectors

A high-performance readout circuit for photoelectric detectors is developed in this paper to achieve high-speed low-noise image detection. Here, the W/L ratio of the first-stage P-type following transistor is reduced to decrease the parasitic capacitance of buses, and the bias voltage of the P-type following load transistor is minimized to increase the driving current. These changes increase the sampling frequency of the read-out circuit from its original 2 MHz to 6 MHz, thereby effectively improving the readout frequency of the long-line visible light CMOS detector. Four-sampling is used to achieve true correlated double-sampling and reduce the equivalent input noise of the device, thus, overcoming the original circuit’s non-true correlation cancellation. Testing revealed that the number of equivalent input noise electrons of the CMOS detector decreased from 100e to 50e (rms) when the integral time is 200 µs and the photosensitive area is 20 × 18 μm2. The device could work steadily at a sampling rate of 6 MHz, and its linearity and output swing exceed 99% and 2 V, respectively. Moreover, the sensitivity of the detector could meet the requirements of the system. The development of the proposed CMOS detector lays an important theoretical foundation and provides practical value for future research on ultra-high speed and high-definition image detection technologies.