Suppressing Stress and Defect Clustering in 8-inch PVT-Grown 4H-SiC Crystals via High-Temperature Post-Growth Annealing

The 8-inch silicon carbide crystals prepared by physical vapor transport (PVT) offer a low-cost pathway for chip production, significantly enhancing the economies of scale. However, point defects， such as vacancies, interstitial atoms, and dislocated atoms produced by the temperature gradient mismatch and the fluctuation of the C/Si ratio during the growth process, seriously affect the residual stresses and the crystalline quality of the crystals. Using stress birefringence optical path difference and X-ray diffraction rocking curve detection methods, we characterized crystals annealed at different temperature. It is well-known that the residual stress of the wafer exhibits an uneven distribution, with the residual stress at the edge of the wafer significantly higher than that at the center. When the post-growth annealing temperature is below 2000°C, the residual stress of the crystal decreases rapidly due to the annihilation and transformation of point defects. However, when the temperature is increased further to 2200°C, a large number of irreparable and large-sized point defect clusters form, which severely degrade the crystalline quality of the crystal, induces lattice distortion, and lead to the generation of residual stress. Overall, the best residual stress relief is achieved at a post-growth annealing temperature of 2000°C.