Investigation of refresh characteristics in 4F 2 vertical DRAM cells for sub-10 nm era

Abstract This study quantifies refresh degradation in 4F² vertical channel dynamic random-access memory (DRAM) cells using technology computer-aided design (TCAD). The vertical architecture forms a floating body due to the absence of a body contact, where gate-induced drain leakage (GIDL) during hold leads to hole accumulation, channel potential elevation, and accelerated storage node voltage (SNV) loss. A buried channel array transistor (BCAT) reference with a body contact maintains stable retention up to 1000 ms by effectively discharging generated holes. In contrast, the vertical DRAM exhibits rapid SNV decay, failing at 19 ms. While drain-side doping underlap can suppress GIDL and improve retention, it significantly degrades on-current. To overcome this trade-off, a modified structure with a shortened back-gate underlap is proposed, achieving retention improvement from 80 ms to 160 ms while preserving drive current. These results provide design guidelines for reliable high-density DRAM cells.