Nodal State Comparison-based Dynamic Hold Technique for Low Power OR Gates in Domino Logic

This paper presents a novel circuit technique NSCDH, to construct OR gates with 8 inputs up to 128 inputs and single output, which can be cascaded to further stages. It uses stage isolation technique to provide current free nodal state comparison with the ability to hold circuit at an optimal state, thereby resulting in 44.6% lesser power consumption and 16.1% higher noise immunity at 8 inputs as compared to CDDK (2019) and 24.4% lesser power consumption at 128 inputs as compared to CDDK (2019). Circuit simulation is done using HSpice. Standard BSIM4 90 nm PTM file is used to model NMOS and PMOS transistors. Circuit schematic is made using LT Spice. OR gates built using this technique can be used in many applications as multiplexers, read–write data paths, memories, and adders.