均衡器
横向(组合学)
控制理论(社会学)
电子工程
建筑
计算机科学
数学
工程类
电信
数学分析
人工智能
频道(广播)
艺术
视觉艺术
控制(管理)
作者
H. Zhang,Enrico Monaco,Matteo Bassi,Andrea Mazzanti
出处
期刊:Electronics Letters
[Institution of Engineering and Technology]
日期:2017-11-03
卷期号:53 (25): 1629-1630
被引量:1
摘要
Transceivers for backplane serial links operating up to 25 Gb/s demand flexible equalisers with high accuracy in matching the channel response. A continuous time linear equaliser (CTLE) with a transversal architecture features variable DC gain and two zeros that can be tuned independently. The transversal architecture yields a paraboloid mean‐square‐error surface, allowing optimal adaptation through gradient descent algorithms. The CTLE was realised in a 28 nm CMOS technology and measurements are presented at data rate from 5 to 25 Gb/s across 20 dB‐loss channels. Core power dissipation is 17 mW from 1 V supply and horizontal eye opening at BER 10 −12 is equal or larger than 50%, comparing favourably against previously reported equalisers targeting similar data‐rate and channel loss.
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