3D to 2D perspectives - Traditional and new doping and metrology challenges at the nanoscale

In this perspectives paper we will explore the doping state-of-the-art as it evolves for 3D to 2D structures and materials, and the following impact on the metrology methods needed to characterise them. Historically, silicon devices for logic complementary metal-oxide-semiconductor (MOS) are built in bulk monocrystalline substrates. In this context bulk silicon substrates are 3D, as there is not the electrostatic confinement associated with more technologically advanced device structures. The determination of technology figures-of-merit such as sheet resistance, impurity concentration and activation profiles versus depth, and reverse bias leakage current to track crystal quality post-doping process, have been the typical methods for evaluation. Since the emergence of FinFET, gate-all-around (GAA) for logic, and layered 2D materials such as transition-metal-dichalcogenides (TMDs) for MOS channel active areas, these figures-of-merit are more awkward to extract, or simply do not apply in the usual sense. Logic devices, like MOS transistors, depend on doping processes to lower access resistance and thus drive performance, traditionally relied on ion implantation to introduce impurities to the substrate, which is a physical bombardment that damages the target material. Gentler doping processes that rely on in-diffusion are an emerging category, and most recently the concept of terminating or functionalising the (near-) surface of the semiconductor is growing in popularity, at least in research labs. Likewise, methods to characterise these require evolution to adapt to the times, from the conventional high-throughput techniques to the more exploratory, albeit lower throughput, methods. Metrology relies upon high-sensitivity, large dynamic range of detection, spatial resolution, as well as time- and cost-efficient sample preparation and post-analysis data interpretation. Driven primarily by the continued development of novel, scaled-down, truly unique device architectures and the introduction of novel materials in the nano-fabrication technology, the portfolio of dopant characterisation methods is unremittingly enlarging its numbers. Herein, we focus our discussion onto dopant profiling for fin and nanowire FETs, and relate these to analysis of test vehicles such as arrays of fin structures with varying dimensions. Although reports detailing correlative use of the dopant characterisation methods are only a few, we present examples that provided unique new information, in absence of which the overall description of the dopant process is inconclusive and, in some cases, misleading.