An Innovative Technique for Large-Scale Delayering of Semiconductor Devices with Nanometric-Scale Surface Flatness

Abstract We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.