A Cascode Current Mirror Based 90 mV to 1.8 V Level Shifter with Alleviated Delay

The chip industry is developing quickly and the demand for faster processors has increased over the years. Level shifters find their major application in processors. In order to increase the speed of the processors, the delay of the level shifters need to be reduced. In order to improvise on the delay parameter and increase the width of the conversion range, a cascode current mirror-based level shifter (CCMLS) is proposed. The proposed CCMLS is implemented and analyzed in Cadence Virtuoso simulator at 45 nm technology. The CCMLS circuit can level shift up voltages from 90 mV to 1.8 V. Pull-up boost is used as a current limiter. It reduces the node voltages without using up too much current. The proposed circuit also makes use of a split-input inverting buffer which helps to improve energy efficiency. The delay of the proposed level shifter is 5.171 ns when the input pulse frequency is 100 kHz. The input pulse, low supply voltage and high supply voltage are 90 mV, 140mV and 1. SV respectively. The output power consumption is 9SS.1mW while the energy per unit transition is 47.16 fJ. The delay has improved by 36.95%, the power by 0.79%, the energy per transition by 99.86% when compared to the robust-high speed energy efficient level shifter from [7].