Layout-Dominated Dynamic Current Imbalance in Multichip Power Module: Mechanism Modeling and Comparative Evaluation

The multichip power module is an irreplaceable component for high-capacity industrial converters. Dynamic current imbalance among parallel chips challenges the electrothermal stability and limits the maximum current rating of the power module. In this paper, general mechanism models are proposed to reveal the layout-dominated dynamic current imbalance in the multichip power module. The influence of the layout on the current sharing is comparatively evaluated by power modules with and without Kelvin connections. Focusing on the dynamic current imbalance, based on a commercial multichip power module, finite-element analysis and equivalent electric circuit are utilized to illustrate the impact of Kelvin connection. General mathematical and graphical models are created to address the current sharing of parallel chips affected by networked parasitic impedances. Based on the fabricated power module prototypes, extensive experiments and detailed analyses are presented concerning the current sharing, transient time, and switching loss. It is demonstrated that the Kelvin connection can elevate switching speed and reduce switching loss of parallel chips, while its functionality to eliminate dynamic current imbalance depends on the parasitic impedances. Some general design guidelines of the multichip power module are presented for current sharing. To achieve satisfactory current sharing, advanced packaging layout by using the optimized chip arrangement and wire interconnection is further needed for the multichip power module.