First principles study of high-performance sub-5-nm monolayer SnS field-effect transistors

<sec>Currently, Si-based field-effect transistors (FET) are approaching their physical limit and challenging Moore's law due to their short-channel effect, and further reducing their gate length to the sub-10 nm is extremely difficult. Two-dimensional (2D) layered semiconductors with atom-scale uniform thickness and no dangling bonds on the interface are considered potential channel materials to support further miniaturization and integrated electronics. Wu et al. [Wu F, et al. <ext-link ext-link-type="uri" xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="https://www.nature.com/articles/s41586-021-04323-3">2022 <i>Nature</i> <b>603</b> 259</ext-link>] successfully fabricated an FET with gate length less than 1 nm by using atomically thin molybdenum disulfide with excellent device performance. This breakthrough has greatly encouraged further theoretical predictions regarding the performance of 2D devices. Additionally, 2D SnS has high carrier mobility, anisotropic electronic properties, and is stable under ambient condition, which is conducive to advanced applications in 2D semiconductor technology. Herein, we explore the quantum transport properties of sub-5 nm monolayer (ML) SnS FET by using first-principles quantum transport simulation. Considering the anisotropic electronic SnS, the double-gated-two-probe device model is constructed along the armchair direction and the zigzag direction of ML SnS. After testing five kinds of doping concentrations, a doping concentration of 5×10¹³ cm^–2 is the best one for SnS FET. We also use the underlaps (ULs) with lengths of 0, 2, and 4 nm to improve the device performance. On-state current (<i>I</i>_on) is an important parameter for evaluating the transition speed of a logic device. A higher <i>I</i>_on of a device can help to increase the switching speed of high-performance (HP) servers. The main conclusions are drawn as follows.</sec><sec>1) <i>I</i>_on values of the n-type 2 nm (UL = 4 armchair), 3 nm (UL = 2), 4 nm (UL = 3), 5 nm (UL = 0) and the p-type 1 nm (UL = 2 zigzag), 2 nm (UL = 2 zigzag), 3 nm (UL = 2, 4 zigzag), 4 nm (UL = 2, 4 zigzag), and 5 nm (UL = 0, armchair/zigzag) gate-length devices can meet the standards for HP applications in the next decade in the International Technology Roadmap for semiconductors (ITRS, 2013 version).</sec><sec>2) <i>I</i>_on values of the n-type device along the armchair direction (31–2369 μA/μm) are larger than those in the zigzag direction (4.04–1943 μA/μm), while <i>I</i>_on values of the p-type along the zigzag direction (545–4119 μA/μm) are larger than those in the armchair direction (0.7–924 μA/μm). Therefore, the p-type ML GeSe MOSFETs have a predominantly anisotropic current.</sec><sec>3) <i>I</i>_on value of the p-type 3 nm gate-length (UL = 0) device along the zigzag direction has the highest value 4119 μA/μm, which is 2.93 times larger than that in the same gate-length UL = 2 (1407 μA/μm). Hence, an overlong UL will weaken the performance of the device because the gate of the device cannot well control the UL region. Thus, a suitable length of UL for FET is very important.</sec><sec>4) Remarkably, <i>I</i>_on values of the p-type devices (zigzag), even with a gate-length of 1 nm, can meet the requirements of HP applications in the ITRS for the next decade, with a value as high as 1934 μA/μm. To our knowledge, this is the best-performing device material reported at a gate length of 1 nm.</sec><sec>5) Subthreshold swing (SS) evaluates the control ability of the gate in the subthreshold region. The better the gate control, the smaller the SS of the device is. The limit of SS for traditional FET is 60 mV/dec (at room temperature). Values of SS for ML SnS FET alone zigzag direction are less than those along the armchair direction because the leakage current is influenced by the effective mass.</sec>