Gate-oxide interface performance improvement technology of 4H-SiC MOSFET

MOSFET devices are one kind of the core devices of modern microelectronics, with applications ranging from highly integrated CMOS chips to high power devices. As a third-generation wide bandgap semiconductor material, SiC has excellent electrical properties such as wide bandgap, high breakdown electric field, and high temperature resistance. The application of 4H-SiC MOSFET devices in power electronics systems can significantly enhance the reliability and reduce the power consumption of the system, which makes 4H-SiC MOSFETs have a wide application prospect in power electronics systems. Nowadays, SiC MOSFETs suffer from low channel mobility, threshold voltage drift, insufficient long-term reliability of the gate oxygen dielectric at high temperatures, and bipolar drift in the forward-guided state of the body diode. Remarkably, many of these problems are related to defects at the gate-oxide interface. Owing to the presence of SiC/SiO₂ interface defects, the channel mobility of SiC MOSFET devices is grossly limited, and the reliability of the gate-oxide layer as well as the stability of the threshold voltage are also significantly affected, contributing to the poor performance of the gate-oxide interface. For instance, partial traps will become charged centers upon electron capture, which leads to enhanced Coulomb scattering effects on the surface of the channel and consequently reduced channel mobility. Decreasing the thickness of the gate-oxide layer can enhance the current driving capability of the transistor and boost the switching speed as well as the power characteristics. However, a thin oxide layer will aggravate the tunneling effect of the electron and make the oxide layer unreliable. To ameliorate these concerns, this review presents a number of processes for gate-oxide interface performance enhancement of 4H-SiC MOSFETs from four aspects: Annealing, utilization of high-k dielectric layers, gate oxide doping, and trench-type MOSFETs’ trench depth-width optimization, along with an analysis of the effects of these processes on 4H-SiC MOSFETs. The annealing process can reduce the defects at the gate-oxide interface to a certain extent, enabling the interface density of states to be diminished and thus enhancing the channel carrier mobility. For a specific gate dielectric thickness, the application of high-k gate dielectric material dramatically reduces the electric field value, thereby reducing the total gate current density and increasing the reliability of the gate-oxide layer. Doping of different ions in the gate oxide is effective in passivating SiO₂/SiC interfacial traps and upgrading carrier mobility. As for trench MOSFETs, according to the influence of breakdown voltage and on-resistance with the change of groove depth and width, better FOM value can be found by continuing to optimize the width and depth of the gate, so as to further promote the reliability of trench MOSFETs. This paper reviews various feasible alternatives from several perspectives in order to further comprehensively improve the performance of 4H-SiC MOSFET gate-oxide interface for better applications in power electronics systems.