A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

分频器 模数 频率合成器 物理 数学 电子工程 电气工程 锁相环 光学 工程类 功率分配器和定向耦合器 几何学 相位噪声
作者
Aditya Narayanan,Abhishek Bhat,Nagendra Krishnapura
出处
期刊:IEEE Journal of Solid-state Circuits [Institute of Electrical and Electronics Engineers]
卷期号:59 (9): 2818-2830 被引量:8
标识
DOI:10.1109/jssc.2024.3373620
摘要

This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). Modulus-dependent delay (MDD) of the feedback divider increases jitter in fractional- $N$ mode. The delay change can exceed 100 ps when the number of stages in the divider chain changes. A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is implemented to overcome this effect. The delay change is turned into a periodic error at half the reference frequency that is then filtered by the loop filter. The prototype synthesizer in 65-nm CMOS occupies 0.54 $\text{mm}^\text{2}$ and consumes 66 mW at the highest frequency from a 1-V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400, 300, and 500 fs in the 6 to 8-GHz, 8 to 10-GHz, and 10 to 12-GHz ranges, respectively. The worst case reference spurs are below $\mathbf{-60}$ dBc and the fractional spurs are below $\mathbf{-31}$ dBc.
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