A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration

High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) typically require bit weight calibration. The bit weight self-calibration technique is extensively used for its fully digital operation and low circuit complexity. Nonetheless, the comparator offset easily saturates the calibration circuit and leads to large bit weight errors in high-resolution scenarios, which needs to be cancelled in the analog domain. Moreover, the calibration needs to be repeated many times to reduce the circuit noise during calibration. These increase circuit complexity and calibration time. In this paper, a 16-bit SAR ADC with dual-segmental bit weight self-calibration is presented. The proposed calibration scheme increases the offset tolerance and suppresses the circuit noise during calibration. Therefore, precise analog-domain offset cancellation is not required, and the calibration time can be reduced. With these merits, the 16-bit SAR prototype designed in a 180-nm CMOS process achieves 16-bit linearity in only 370 clock cycles for calibration. The offset tolerance also increases to 7.5 mV. The extra analog circuit overhead for calibration reduces from high-resolution analog offset compensation circuits to only a comparator with a much-relaxed precision requirement, preserving the simple and scaling-friendly nature of SAR ADCs. With a sampling capacitance of 7 pF, the SAR ADC converts the signal at 4 MS/s with a peak signal-to-noise-and-distortion-ratio (SNDR) and a peak spurious-free dynamic range (SFDR) of 87.5 dB and 102 dBc, respectively. It consumes 10.1 mW from both 1.8-V and 3-V supplies and achieves a Schreier-figure-of-merit (FoM) of 170.5 dB at 4 MS/s.