材料科学
微电子
平版印刷术
纳米技术
制作
自组装
节点(物理)
晶体管
共聚物
多重图案
集成电路
纳米
PMOS逻辑
光电子学
计算机科学
纳米-
块(置换群论)
纳米尺度
作者
Chi-Chun Liu,Elliott Franke,Yann Mignot,Ruilong Xie,Chun Wing Yeung,Jingyun Zhang,Cheng Chi,Chen Zhang,Richard A. Farrell,Kafai Lai,Hsinyu Tsai,Nelson Felix,Daniel Corliss
标识
DOI:10.1038/s41928-018-0147-4
摘要
The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling—the process of reducing transistor dimensions and increasing their density in microchips—a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology. A comparison between the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nm node FinFETs shows similar device performance, suggesting directed self-assembly could offer a simplified patterning technique for future semiconductor technology nodes.
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